As is known, BCD power technology enables integration of structures of different types in a same chip. This technology has enjoyed wide application thanks to integration of circuitry transistors defining an intelligent part with power components.
Consequently, in view of the continuous requirements of miniaturization, it is desirable to modify the present process flow, so as to reduce the dimensions of the devices, and specifically of the DMOS transistors.
In particular, it is desirable to reduce the size between the source contact and the gate region of the DMOS transistor, without causing at the same time any critical factors in the performance of the device or of the fabrication process.
On the other hand, a mere reduction of the dimensions and distances between the various parts without modifying the layout of the device would entail the risk of errors in the positioning of the various regions or superposition thereof on account of the tolerances of fabrication, and hence of malfunctioning of the device.
The aim of the present invention is to solve the problems referred to above.